Importing KiCad and EAGLE projects
At a glance
- Import complete KiCad 6–10 and EAGLE 6+ XML projects, boards and libraries
- Preflight names unsupported or missing content before the project changes
- Keep supported placement and copper, or retain schematic and mechanics for a fresh JC3 layout
- A SHA-256 source-closure check rejects files that changed after inspection
- Fusion Electronics projects use a complete local EAGLE XML export; cloud-only libraries must be supplied
Use Import → Import KiCad Project / Library or Import EAGLE / Fusion Project / Library. The first step is always an inspection. It reads the complete local source closure, compares schematic and board evidence, and gives every unsupported or lossy construct a named finding.
Supported sources
KiCad 6 through 10 project, schematic, PCB, symbol, footprint and complete .pretty library sources are tested. EAGLE 6+ XML .sch, .brd and .lbr sources are supported, including matching local Fusion Electronics exports.
Legacy binary EAGLE needs to be saved as EAGLE 6+ XML first. A Fusion cloud project needs a complete local export. A managed library that exists only in the cloud is reported as missing; JetCad3 does not sign into Fusion or guess its contents.
Choose what to retain
Complete Project keeps supported hierarchy, parts, board mechanics, placement, routing, zones and rules. Relayout in JC3 keeps the schematic, parts and board mechanics while leaving copper for JetCad3's native layout workflow. Libraries Only is available for library sources.
You can add a board, replace the matching imported board, or explicitly replace the active board. The source files stay read-only.
Compare the imported PCB
Footprint placements, pad rotations and top/bottom copper follow the KiCad board. References, values and other footprint text retain their source positions, layers, visibility, mirroring and keep-upright settings. Through-hole pads and mounting holes remain visible from either side.
To compare both sides at once, enable Other side in the board view controls. Enable the desired silkscreen, fabrication and courtyard layers in the browser. Ratsnest shows airwires where copper has not yet joined a net's pads. Existing traces, vias and available filled copper remove connections from the ratsnest automatically. Editing the board starts a new connection check; the status shows when that check is pending, unavailable or incomplete. Zero airwires does not replace DRC or resolve missing copper fill. Traces have round caps and joins, and curves stay smooth as you zoom in.
Older imports need a fresh import to recover corrected schematic pin orientation, copper net identities, PCB placement, layer and text data. Save your existing edits before replacing the board.
Findings are part of the design
A finding can block the import or allow an engineering import while blocking fabrication. Missing definitions, unsupported layers or vias, incomplete outlines, invalid zone geometry and physical pin/net mismatches never disappear during conversion.
Inspection records a SHA-256 digest over the source closure. Apply rereads the files and refuses the operation if any byte changed. After import, review the physical pin map, board outline, placement, copper, fill, DRC and populated-board model coverage before preparing fabrication output.