PCB rules and design checks
At a glance
- One effective rule set drives manual routing, autorouting, copper fill, DRC and fabrication
- Independent connectivity is rebuilt from pads, traces, plated vias and current fills
- Critical nets cover allowed layers, width, length, vias, reference planes and decoupling evidence
- Differential pairs track gap, skew, uncoupled length and matched transitions
- Missing physical evidence reports unchecked; a clean geometric DRC cannot certify a pinout
Open Run PCB Design Rules Check… from the board or browser tree. The check uses the same effective clearances and widths as routing and fill, then independently rebuilds physical connectivity from the generated copper geometry.
What it checks
DRC covers board and cutout boundaries, copper clearances, widths, drill and annular-ring rules, placement/assembly clearances, open connections and shorts. Current copper fills participate in connectivity only while their source fingerprint matches the board.
Critical Signal Constraints adds allowed layers, required width, length and via limits, differential-pair gap/skew/uncoupled limits, matched transitions, reference-plane review, decoupling placement and isolated-domain clearances. Impedance results are documented estimates over reviewed stackup assumptions; they are not field-solver certification.
Passed, failed, unchecked and stale
A declared requirement passes only when enough physical evidence exists to evaluate it. A missing reviewed layer depth, missing model or unsupported analysis reports unchecked. Optional limits you did not configure report not applicable. A board edit makes the previous report stale.
Physical pin mapping has its own independent evidence. ERC and DRC can agree with a footprint whose pads were numbered backwards, so fabrication preflight also requires a verified terminal-to-pad map.